Design Verification Engineer

Role Overview

We are seeking a highly experienced Design Verification Engineer to join Altera's Design Verification organization. In this critical role, you will be responsible for verifying the correctness, performance, and compliance of FPGA and SoC designs, with a strong focus on PCIe subsystems.

What You Will Do

Develop, implement, and maintain comprehensive UVM-based testbenches for PCIe IP, subsystems, and full-chip FPGA/SoC designs. Define and own the verification plan for assigned design blocks, covering functional coverage, code coverage, assertions, and protocol compliance checks.

Why It Might Be a Fit

This is a senior individual contributor role requiring deep domain expertise in functional verification methodologies, PCIe protocol compliance, and advanced simulation and formal techniques. You will have significant influence over verification architecture decisions and be expected to mentor junior engineers on best practices.

Requirements

• Bachelor's Degree in Electrical Engineering, Computer Engineering, or a closely related technical discipline
• 8+ years of professional Design Verification experience in the semiconductor or FPGA industry
• 4+ years of hands-on experience verifying PCIe IP or subsystems
• 7+ years of experience writing SystemVerilog and UVM-based testbenches
• 4+ years of experience developing constrained-random test environments for complex SoC or FPGA designs

Benefits

• Salary range: $142.6K - $206.5K USD
• Incentive opportunities
• Health insurance
• Paid time off
• Retirement plan