Senior Design Verification Engineer

Role Overview

Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.

What You Will Do

Develops robust verification environments, creates and implements test cases, and utilizes SystemVerilog Assertions to enhance bug detection.

Why It Might Be a Fit

Requires expertise in HDL, HVL, UVM, and modern verification methodologies, with strong analytical, problem-solving, and debugging skills.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 9+ years of experience in ASIC or FPGA design verification
• Expertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as SystemVerilog
• Strong hands-on experience in developing UVM-based testbenches and verification components
• Proficiency in modern verification methodologies, including coverage-driven verification (CDV) and assertion-based verification (ABV)
• Familiarity with industry-standard protocols such as AMBA (AXI, ACE, CHI, APB), PCIe, or Ethernet
• Experience with simulation and debug tools
• Strong scripting skills in Python, Perl, or Tcl for automation and data analysis
• Excellent analytical, problem-solving, and debugging skills
• Strong communication skills and the ability to work effectively in a collaborative, cross-functional team environment