Principal Engineer, Physical Design

Lead end-to-end RTL-to-GDSII execution for a given SoC program, driving synthesis, floorplanning, placement, CTS, routing, and signoff to achieve predictable tapeouts. Partner with RTL, DFT, packaging, and system teams to align design, testability, and manufacturability goals across the product lifecycle.

Requirements

• B.Tech/M.Tech (or higher) in Electrical/Electronics Engineering or related field.
• 12+ years in physical design with a proven track record of successful tapeouts of complex, high-performance SoCs across advanced nodes.
• Deep expertise in full-chip physical design, including floorplanning, power planning, placement & routing, clock architecture/CTS, extraction, and full signoff methodologies.
• Proficiency in TCL, Python, or similar scripting, with a track record of driving automation and partnering with CAD teams for flow enhancements.
• Strong collaboration with RTL, DFT, packaging, product, and system teams to align on design, test, and manufacturing goals.
• Excellent communication skills with the ability to operate effectively in global, cross-functional environments.