Senior DFT Engineer

The Senior DFT Engineer will design and implement DFT specifications, architecture, and implementation using state-of-the-art methodologies and tools. Responsibilities include supporting all product lines with high coverage, low power, and low test time, and delivering high-quality, verified ATPG patterns.

Requirements

• 6-8 years of directly related experience in ASIC/SoC DFT
• Expert level knowledge of DFT architecture and planning
• Hands on Tessent DFT Tool experience
• Expert level knowledge of Scan, Test Compression, At-Speed Test, Memory Built-In Self-Test (MBIST), Logic Bist (LBIST)
• Scripting: Perl/Python/Tcl
• Strong written and verbal communication skills