Design Verification Engineer

This design verification engineering role involves ensuring bug-free silicon for a specific SoC or IP, developing verification methodologies, and leveraging LLMs for efficient verification processes. Responsibilities include creating test plans, developing infrastructure, validating designs, debugging, and measuring coverage. The role aims to build scalable and portable verification environments.

Requirements

• Study design specification and create test plan
• Develop infrastructure in SystemVerilog/UVM to stress the design
• Develop and fix failures from regressions
• Use LLMs to do verification efficiently
• BS degree in technical subject area with 3+ years of proven experience or equivalent
• Strong knowledge of OOP, SystemVerilog and UVM
• Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection
• Some working experience using LLMs for efficiency and quality

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Tuition reimbursement
• Discretionary bonuses
• Relocation