Design Verification Engineer - Power Management (m/f/d)

This design verification Engineer role focuses on building and maintaining verification test benches for power management systems. The engineer will develop verification plans, generate random tests, analyze coverage, and improve the verification flow. They will use hardware description languages and simulator to verify complex designs and ensure a flawless verification process.

Requirements

• Strong knowledge of SystemVerilog and UVM
• Experience developing scalable and portable test-benches
• Experience with constrained random verification environments
• MS/BS in Computer Science or Electrical Engineering or equivalent
• Fluency in English language
• Basic knowledge of mixed signal verification