We are looking for a world-class Memory Subsystem Architect to join our SoC team at Baidu's Sunnyvale office. The successful candidate will provide technical leadership through all phases of Baidu's AI SoC development, primarily focused on unified memory space architecture design for Baidu AI accelerator SoC.
Requirements
- 10+ years of experience in Silicon architecture or IP design mainly focusing on memory subsystem
- Strong understanding of distributed AI training system's requirement on SoC memory subsystem
- Demonstrated experience in HW digital design and understanding of CPU/HW Accelerators and/or Peripheral design
- Familiarity with SW and Operating system practices and requirements on memory system
- Experience in System Performance analysis and debug in pre and/or Post-Silicon environments
- Solid background of System interconnect, System MMUs, Caches and Memory Technologies (e.g. HBM, GDDR, DDR and LPDDR4/5)
- Experience with data analysis using Excel, Perl, Python etc.
- Master or PhD in Electrical or Computer Engineering
- Excellent communication skills in both English and Chinese
Benefits
- Mission alignment
- Self-directed
- Hungry to learn
- Team orientation
