R&D Engineer IC Design

The Engineer will be responsible for verification of complex switch designs, creating SystemVerilog-based verification environments and creating and executing testplans for verifications of RTL and gatesim-based designs.

Requirements

• A Master's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent
• A minimum of 6 years of work experience in Design Verification
• Strong knowledge and hands-on experience in verification methods, tools and environment
• Strong programming skills, including in System Verilog and scripts languages
• Knowledge and experience in UVM methodology is preferable
• Knowledge of networking and switching concept is a plus

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave
• Vacation time
• Paid Family Leave