Cadence Design Systems Inc. is looking for a Pre-Silicon Verification Engineer with extensive experience in function verification and a passion for leveraging artificial intelligence to redefine the verification landscape.
Requirements
- BS with a minimum of 4 years of experience OR MS with a minimum of 2 years of experience OR new PhD Graduate
- Proven expertise of more than 3 years in at least one of the pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM
- Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools
- Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC)
- Strong programming skills in Verilog, System Verilog and Python
- Excellent communication skills and the ability to thrive in a team-oriented environment
- Self-motivated, with a proactive approach to problem solving, continuous learning, and innovation
Benefits
- Employee-friendly policies focus on physical and mental well-being, career development, and learning opportunities
- One Cadence – One Team culture promotes collaboration and customer success
- Multiple avenues of learning and development available for employees
- Diverse and talented team of passionate and dedicated individuals
