Lead Design Engineer position at Cadence in Bangalore, working on RTL coding, datapath designs, and complex FIFO design.
Requirements
- Proficient in RTL coding, datapath designs, complex FIFO design
- Strong knowledge on complete design flows and rigorous checks before delivery to other teams or customers
- Good experience of micro architecture, design, synthesize for a complex SerDes IP in various technology nodes
- Desired Protocols knowledge – USB, PCie, MIPI(DPHY), HDMI/Display
- Good understanding of working with signal processing IPs in terms of knowing calibrations, plls, dividers
- Ability to work closely with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits
Benefits
- Competitive salary and benefits package
- Opportunities for professional growth and development
- Collaborative and dynamic work environment