Lead Design Engineer

Lead Design Engineer position at Cadence, responsible for developing firmware for DDR/LPDDR/GDDR/HBM PHY using microcontrollers, collaborating with hardware designers and memory subsystem architects, and debugging firmware-based simulations.

Requirements

• 4-6 years of experience in developing bare-metal firmware for High-speed Serdes or Memory interface Physical Layer blocks
• Good Knowledge C programming language for embedded software development and use of relevant IDE
• Good debugging skills
• Good experience on Verification EDA Tools like simulators and waveform viewers
• Good communication Skill