Lead Design Engineer

Lead Design Engineer at Cadence, working on cutting-edge technology, collaborating with diverse team, and promoting innovation.

Requirements

• 5+ years experience with B.E/B.Tech or M.E/M.Tech
• Strong background in functional verification fundamentals, verification environment planning & development, test plan creation
• Prior Digital verification experience in some of the serial bus multiprotocol PHY IP’s (such as SerDes, USB/DPHY,UCIe)
• Strong expertise in Verilog, HVL(SV, e) with UVM methodology
• Experience in assertions development/closure, constraint randomization, functional coverage, code coverage
• Strong RTL and GLS debug skills

Benefits

• Employee-friendly policies
• Multiple avenues of learning and development
• Diverse team of passionate, dedicated, and talented individuals