Lead Design Engineer

Lead Design Engineer at Cadence in Bangalore, responsible for developing firmware for DDR5 PHY using microcontrollers, collaborating with hardware designers and verification team, and debugging firmware in RTL based hardware simulations.

Requirements

• Good Knowledge of DDR5 JEDEC spec
• Relevant experience in developing bare-metal firmware for High-speed SerDes or Memory interface Physical Layer blocks
• Good Knowledge of C programming language for embedded software development
• Comfortable debugging RTL simulations involving firmware and microcontroller subsystem
• Good knowledge of Shell/Perl/Python/TCL scripting
• Good experience on Verification EDA Tools like simulators and waveform viewers