Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We're looking for a Principal Design Engineer with 8+ years of Design Verification experience.

Requirements

• BE/BTech/ME/MTech degree in Electrical / Electronics / VLSI
• 8+ years of Design Verification experience with SV/UVM
• Strong background on functional verification fundamentals, environment planning, test plan generation, environment development
• Design Verification experience verifying complex designs and leading projects from concept to verification closure
• Strong hands-on UVM and System Verilog coding experience and functional verification environment development
• Prior experience in IP verification of memory IP (DDR/HBM/GDDR) is an added advantage