Principal Product Validation Engineer

Cadence is hiring a Principal Product Validation Engineer with expertise in Electrical, Electronics, or Computer Science, and experience in simulation/emulation, EDA tools, process automation, and SystemVerilog. The role requires designing and implementing complex functional verification environments, with knowledge of protocols like PCIe, USB3/4, and DP.

Requirements

• Electrical, Electronics, or Computer Science Engineer
• Very good understanding of HDLs (Verilog and/or VHDL)
• Experience in simulation/emulation using HDLs
• Good working knowledge of EDA tools (Cadence/Others)
• Experience with process automation with scripting
• Experience with SystemVerilog, C++, UVM
• Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog
• Experience designing and implementing complex functional verification environments
• Knowledge of protocols like PCIe, USB3/4, DP