Sr Principal Design Engineer

We hire and develop leaders and innovators who want to make an impact on the world of technology. The role requires management of a Memory Controller DV group focusing on MDV verification and customer interactions.

Requirements

• At least 11+ years of relevant experience including design verification experience.
• Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
• Strong expertise in Verilog, SV with UVM methodology.
• AXI and/or CHI experience is highly desirable.
• Prior experience in leading and managing teams with expertise in any of DDR, PCIe, UCIe or USB is strongly required.
• Memory controller verification experience is a plus.

Benefits

• Multiple avenues of learning and development available for employees to explore
• Employee-friendly policies focus on physical and mental well-being
• One Cadence – One Team culture promotes collaboration
• Diverse team of passionate, dedicated, and talented individuals