Sr Principal Design Engineer

We are seeking a highly skilled RTL Design Engineer with expertise in PCIe protocol (Gen4/Gen5/Gen6) to join our PCIe Controller IP development team.

Requirements

• Architect and implement RTL for PCIe IP blocks
• Collaborate with system architects to define micro-architecture and design specifications
• Responsible for the quality of Design Quality
• Work closely with verification teams to develop testbenches and validate functionality
• Participate in interoperability testing
• Contribute to performance, power, and area optimization in advanced nodes
• Interface with cross-functional teams including PHY, software, and validation