Sr Principal Product Validation Engineer

The Sr Principal Product Validation Engineer should have experience in simulation/emulation using HDLs (Verilog and/or VHDL), good working knowledge of EDA tools, and experience with process automation with scripting.

Requirements

• Electrical, Electronics or Computer Science Engineer
• Good understanding of HDLs (Verilog and/or VHDL)
• Prior experience in simulation/emulation using HDLs
• Good working knowledge of EDA tools (Cadence/Others)
• Experience with process automation with scripting
• Experience with SystemVerilog, C++, UVM
• Experience with Functional Verification of complex digital systems
• Experience designing and implementing complex functional verification environments