Sr Principal Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. As a Principal Verification Engineer, you will be responsible for scheduling, designing, developing, and supporting UVM-based verification environments, processes, and methodologies for IP models of system level memory such as SDRAM (LPDDRx, DDRx, HBMx), DFI PHY, UFS, and complex storage memory models for use on hardware-based verification products.

Requirements

• BS/MS degree in EE or CS
• 5-7+ years of experience in relevant experience
• Expert understanding of HDLs and HVLs such as Verilog and SystemVerilog
• Solid experience in simulation/emulation using these languages
• Expert working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/verification problems using these tools
• Deep experience with UVM, SystemVerilog, and C++
• Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog
• Experience with Functional Verification of complex protocol-based blocks—e.g. UFS / Unipro/ MPHY verification—with a Hardware Verification Language (HVL) like SystemVerilog
• Experience designing and implementing complex functional verification environments
• Experience in process automation with scripting

Benefits

• Generous Paid Time Off
• 401k Matching
• Retirement Plan
• Visa Sponsorship
• Four Day Work Week
• Generous Parental Leave
• Tuition Reimbursement
• Relocation Assistance