Cadence is seeking a Sr Principal Verification Engineer to contribute to the application of machine learning techniques in pre-silicon functional verification methodologies, develop agentic AI solutions, and engage with customers to deliver innovative verification strategies.
Requirements
- Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.
- Proven expertise of more than 12-15 years in at least one of the pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM.
- Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools.
- Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC).
- Strong programming skills in Verilog, System Verilog and Python
- Excellent communication skills and the ability to thrive in a team-oriented environment.
- Self-motivated, with a proactive approach to problem solving, continuous learning, and innovation.
Benefits
- employee-friendly policies focus on the physical and mental well-being of employees
- career development
- providing opportunities for learning
- celebrating success in recognition of specific needs of the employees
- multiple avenues of learning and development
- diverse team of passionate, dedicated, and talented individuals
