ASIC Engineer

Role Overview

Join the Physical Design CAD & Methodology Team to develop and support RTL-to-GDS Physical Design implementation and signoff flows across multiple ASIC programs. The team works closely with Physical Design, STA, Power, Physical Verification, and Front-End teams to enable efficient execution, consistent QoR, and reliable tape-outs.

What You Will Do

As a Physical Design Flow & Methodology Engineer, you will take end-to-end ownership of key portions of the PD flow, contributing to implementation and signoff methodology from synthesis handoff through GDS delivery. You will develop, enhance, and maintain block- and chip-level PD flows, debug timing, power, congestion, and physical verification issues, and work closely with design teams to improve convergence and predictability.

Why It Might Be a Fit

This role is a great fit for engineers who combine hands-on technical depth with a growing sense of ownership, collaboration, and continuous improvement. You will have direct impact on QoR, turnaround time, and tape-out success, while allowing you to grow toward senior-level technical leadership.

Requirements

• Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of experience in ASIC Physical Design, PD flow/methodology, or CAD engineering
• Hands-on experience with Physical Design implementation and tools, such as: Fusion Compiler or Innovus, PrimeTime or Tempus
• Strong understanding of RTL-to-GDS Physical Design flow, including synthesis handoff, placement, CTS, routing, and ECOs
• Solid experience with timing, power, and physical verification signoff
• Proficiency in at least one scripting language (Tcl, Python, or Shell)
• Ability to independently debug flow, tool, and QoR issues and propose improvements

Benefits

• Competitive salary
• Equity
• Healthcare
• PTO
• Retirement
• Learning budget
• Parental leave
• Wellness
• Visa/relocation
• Remote flexibility
• Stipends
• Bonus/commission
• Paid holidays