ASIC Engineering Design Verification Leader

Role Overview

Join Cisco's Client Optics Group (COG) as a Verification Engineer to design, develop, and test advanced pluggable and Co-packaged Optics (CPO) for high-speed optical transceivers and platforms. Work with a diverse team of engineers to create verification documentation, develop testbench components, and run verification at block and chip levels.

What You Will Do

Develop testbench components, create verification documentation, run verification at block and chip levels, develop functional coverage models, and debug complex verification issues within a UVM-based framework.

Why It Might Be a Fit

Must have 12-16 years of functional verification experience, strong skills in SystemVerilog, Python, C, and UVM methodology, and good understanding of RTL digital design and DFT principles.

Requirements

• Bachelor’s or Masters in Electronics Engineering (or equivalent/related)
• 12-16 years of functional verification experience
• Strong skills in SystemVerilog, Python, C, and UVM methodology
• Familiarity with UVM phases, configuration mechanisms, factory overrides, and reuse across block, subsystem, and SoC-level verification
• Good understanding of CPU sub-systems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & Protocols
• Experience with RTL design, simulation tools, (e.g., Synopsys, Cadence, Mentor Graphics) and ASIC design flow

Benefits

• Unparalleled security, visibility, and insights across the entire digital footprint
• Opportunities to grow and build are limitless
• Collaborative work environment with a worldwide network of doers and experts