ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Role Overview

Join Cisco's Client Optics Group (COG) as a Verification Engineer to design, develop, and test advanced pluggable and Co-packaged Optics (CPO) solutions. Work with a diverse team of engineers to create verification documentation, develop testbench components, and run verification at block and chip levels.

What You Will Do

Develop testbench components for Silicon Photonics subsystems, build UVM components, and implement constrained-random and directed test strategies. Analyze coverage, add scenarios to enhance coverage, and debug functional simulations.

Why It Might Be a Fit

Must have 8-12 years of functional verification experience, strong skills in SystemVerilog, Python, C, and UVM methodology. Good understanding of CPU sub-systems, FPGA, ODSP, and integrated transceiver features.

Requirements

• Bachelor’s or Masters in Electronics Engineering (or equivalent/related)
• 8-12 years of functional verification experience
• Strong skills in SystemVerilog, Python, C, and UVM methodology
• Familiarity with UVM phases, configuration mechanisms, factory overrides, and reuse across block, subsystem, and SoC-level verification
• Good understanding of CPU sub-systems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & Protocols
• Experience with RTL design, simulation tools, (e.g., Synopsys, Cadence, Mentor Graphics) and ASIC design flow

Benefits

• Competitive salary
• Equity
• Healthcare
• PTO
• Retirement
• Learning budget
• Parental leave
• Wellness
• Visa/relocation
• Remote flexibility
• Stipends
• Bonus/commission
• Paid holidays