Power Optimization Engineer

Power Optimization Engineer responsible for developing chip power model, estimating power consumption, and devising power saving techniques. Works closely with multiple teams to implement optimal power design.

Requirements

• Experience in power optimization using dynamic voltage and frequency scaling techniques
• Experience with gate-level power optimization through VCD-based and/or FSDB-based power analysis
• Strong understanding of concepts of energy consumption, estimation, data movement, low power design, and power-saving features

Benefits

• Full medical, dental, and vision packages
• Housing subsidy of $2,000/month
• Daily lunch and dinner
• Relocation support