Senior ASIC Design Verification Engineer

Role Overview

Drive advanced verification using UVM methodology to validate complex ASIC features. Architect and develop block, subsystem, and full-chip verification environments using SystemVerilog and UVM. Define, design, and execute verification plans and test suites for ASICs.

What You Will Do

Perform verification using simulation tools (VCS / NC-Sim or equivalent). Own end-to-end verification of large ASIC blocks, including coverage analysis and tape-out sign-off. Perform functional coverage, code coverage, and gate-level simulations (GLS). Collaborate with RTL designers for debugging and software teams for bring-up and validation.

Why It Might Be a Fit

15+ years of experience in ASIC Verification using SystemVerilog. Strong expertise in UVM (preferred), OVM, or VMM methodologies. Experience in constrained-random verification. Hands-on experience with ASIC debugging and problem-solving.

Requirements

• 15+ years of experience in ASIC Verification using SystemVerilog
• Strong expertise in UVM (preferred), OVM, or VMM methodologies
• Experience in constrained-random verification
• Hands-on experience with ASIC debugging and problem-solving
• Proficiency with simulation tools like VCS / NC-Sim
• Strong scripting skills in Perl / Tcl (Python is a plus)
• Exposure to networking protocols (e.g., Ethernet) is desirable
• Demonstrated technical leadership and ownership mindset
• B.E/B.Tech or M.E/M.Tech in Electronics or related field

Benefits

• Health & Wellbeing
• Personal & Professional Development
• Unconditional Inclusion