Senior ASIC Design Verification Engineer

Senior ASIC Design Verification Engineer role at Hewlett Packard Enterprise in Bengaluru, Karnātaka, India. The job involves driving advanced verification using UVM methodology, architecting and developing verification environments, and owning end-to-end verification of large ASIC blocks. The ideal candidate should have 15+ years of experience in ASIC Verification using SystemVerilog and strong expertise in UVM methodologies.

Requirements

• Drive advanced verification using UVM methodology to validate complex ASIC features
• Architect and develop block, subsystem, and full-chip verification environments using SystemVerilog and UVM
• Define, design, and execute verification plans and test suites for ASICs
• Perform verification using simulation tools (VCS / NC-Sim or equivalent)
• Own end-to-end verification of large ASIC blocks, including coverage analysis and tape-out sign-off
• Perform functional coverage, code coverage, and gate-level simulations (GLS)
• Collaborate with RTL designers for debugging and software teams for bring-up and validation
• Enhance verification infrastructure through automation using Perl, Python, or Shell scripting

Benefits

• Health & Wellbeing
• Personal & Professional Development
• Unconditional Inclusion