Mixed Signal Logic Design Engineer

The Memory PHY Group (MPG) is looking for a Logic Design Engineer to work on high-speed digital design targeted towards low power optimized IP implementations for the cutting-edge DDRPHY IPs.

Requirements

• Defining architecture and microarchitecture features of the block being designed
• Implementing RTL in System Verilog
• Setting up Automation flows for IP Logic Design
• Ensuring RTL quality via Front End tools for Lint, CDC, RDC, Voltage domain crossings, Synthesis QA checks
• Creating FE packages for IP milestones that meet SoC Collateral requirements
• Creating innovative automated solutions to help Logic Design in areas like Coverage closure, timing convergence etc

Benefits

• Competitive salary
• Benefits package
• Opportunities for career growth