SoC/IP Design Verification Engineer

We're looking for a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. The candidate will own verification planning, UVM testbench development, test content creation, and debug across block, subsystem, and SoC levels.

Requirements

• Verification planning
• UVM testbench development
• Test content creation
• Debugging across simulation and emulation
• Coverage closure
• Assertion-based verification
• Formal verification

Benefits

• Competitive salary
• Benefits package
• Opportunities for growth and development