Principal Engineer - Digital IC Design

Role Overview

Marvell's high-speed DSPs are at the forefront of developing a PAM/Coherent ecosystem, providing low-power, high-performance solutions for cloud data center infrastructure, service providers, AI networks, enterprises, and 5G. The team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell.

What You Will Do

Define the sub system architecture, micro-architecture and register specifications for highly complex SoCs. Drive and participate in specification writeup, develop overall efficient RTL using (System)Verilog, synthesis, and backend resources, integrate internal and external vendor IPs, design, debug, and support ICs, IPs and block DFT, ensuring all quality criteria is met.

Why It Might Be a Fit

Candidate must have a MS/PhD degree in EE or related technical field(s) and 10 years of related professional experience. Fluent in RTL coding design techniques, experience working with multi-clock designs, experience on synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.

Requirements

• MS/PhD degree in EE or related technical field(s)
• 10 years of related professional experience
• Fluent in RTL coding design techniques
• Experience working with multi-clock designs
• Experience on synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification

Benefits

• Competitive compensation
• Great benefits
• Workstyle within an environment of shared collaboration, transparency, and inclusivity
• Tools and resources to succeed in doing work that matters
• Opportunities for growth and development