
Job description
The Marvell post silicon validation group designs and develops test platforms for validating multi-core Arm-based Network processors and custom ASIC’s, used in many communication infrastructure applications such as 5G base stations, NICs, Data Center and Cloud Computing platforms. The electrical characterization team is a post silicon validation sub-group focused on the debug and characterization of SERDES interfaces for various applications on the products.
Complete responsibility for PCIe or Ethernet PHY validation in a post-silicon environment. Define, document, execute, and report the overall PHY validation/test plan for Marvell storage devices. Lab-based silicon bring-up and unit test execution focused on Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the stack.
Strong understanding of high-speed SERDES, equalization techniques, and PCIe or Ethernet protocols. 5+ years of experience with High Speed IO testing, debugging, and validation. 5+ years of direct experience in SERDES characterization/design.
Company

Tech, Software & IT Services
Marvell is a global semiconductor company that designs and manufactures advanced infrastructure solutions for connectivity, storage, and data center workloads. Its portfolio spans wireless and wired connectivity, enterprise and consumer solutions, cloud infrastructure, and high-performance storage. Marvell differentiates itself through an end-to-end design approach that integrates silicon, software, and services, enabling partners to accelerate product development and achieve superior performance. The company emphasizes collaborative engineering, agile partnerships, and a culture that prioritizes execution and innovation, fostering a workplace where employees collaborate closely with customers to deliver tailored solutions.
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