Senior ASIC DFT Engineer

Role Overview

As a Senior ASIC DFT Engineer, you will implement DFT for Micron IPs and Memory controllers (SOC) developed for different types of Storage products. You will work closely with Design (RTL), DV, Physical Implementation team, Test Engineering and Product Engineering team to support early analysis to the Silicon bring-up and Characterization.

What You Will Do

You will be accountable for innovative DFT implementation (Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level. You will generate and validate ATPG patterns using simulations and work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation.

Why It Might Be a Fit

You will have the opportunity to work with a growing team in Hyderabad or Bangalore and be rewarded with multiple Micron benefits, including PTO and medical benefits.

Requirements

• Bachelor's or Master's Degree or equivalent experience in Electronics Engineering, Microelectronics, Software Engineering or a related field
• 5+ years of industry experience with shown ability in DFT of highly sophisticated SOCs
• Experience with Siemens, Synopsys and/or Cadence Cad tools
• Experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python

Benefits

• PTO
• Medical benefits