Senior DRAM RTL design engineer

Design digital IP blocks from initial microarchitecture to RTL creation, integration, and supporting physical hardware development, and drive innovation into future memory generations and design methodology.

Requirements

• Master’s degree in electrical or computer engineering
• 3 - 6 years of experience in RTL design
• Solid knowledge of asynchronous and synchronous design concepts and CDC methodologies
• Deep understanding of SoC design flows (Lint, CDC, synthesis, STA, power analysis)
• Fundamentals in CMOS circuit design, device physics and memory operation
• Ability to work effectively with global multi-functional teams