Staff DRAM RTL design engineer

Staff DRAM RTL design engineer responsible for designing digital IP blocks, defining module interfaces, and collaborating with CAD, EDA, and software teams. Drives full-chip integration and oversees layout process. Performs verification and contributes to cross-group communication.

Requirements

• Master’s degree in electrical or computer engineering
• 6-10 years of experience in RTL design
• Solid knowledge of asynchronous and synchronous design concepts and CDC methodologies
• Deep understanding of SoC design flows (Lint, CDC, synthesis, STA, power analysis)
• Fundamentals in CMOS circuit design, device physics and memory operation
• Ability to work effectively with global multi-functional teams

Benefits

• Health insurance
• Retirement plan
• Paid time off