Digital Verification Engineer

We are looking for a Digital Verification Engineer with 3+ years of experience in verifying digital blocks, building UVM based testbenches, and debugging RTL & Gate level simulations. The ideal candidate will have a Bachelor's degree in Electrical Engineering or equivalent experience.

Requirements

• 3 years minimum experience in Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies
• Extensive experience in verifying digital blocks, building UVM based testbenches, and debugging RTL & Gate level simulations
• Experience in debugging RTL & Gate level simulations