Senior DFT Engineer

onsemi is seeking a DFT Engineer to support the design and implementation of Design-for-Test features for complex ASIC/SoC products.

Requirements

• Develop and integrate DFT architectures including Scan, ATPG, MBIST, and JTAG
• Implement and debug DFT logic to ensure high fault coverage and test quality
• Generate and analyze ATPG patterns using industry-standard tools
• Support at-speed and transition fault testing
• Collaborate with RTL, Physical Design, STA, and Test Engineering teams
• Address timing, CDC, and low-power DFT considerations
• Support test coverage analysis, DFT signoff, and silicon bring-up

Benefits

• Generous Paid Time Off
• 401k Matching
• Retirement Plan