Senior Digital Design Engineer (FPGA/ASIC)

Paradromics is building a brain-computer interface (BCI) platform that records brain activity at the highest possible resolution: the individual neuron. The company is seeking a Senior Digital Design Engineer to translate algorithms and system requirements into clear digital microarchitectures and high-quality, synthesizable RTL that forms the foundation of their silicon.

Requirements

• Define digital microarchitecture for datapaths, control, buffering, and interfaces.
• Write high-quality, synthesizable RTL for FPGAs and ASICs.
• Own FPGA implementation end-to-end: synthesis, timing/physical constraints, implementation, timing closure, and board-level debug.
• Translate DSP algorithms into efficient, real-time hardware pipelines.
• Produce clear interface specs, block diagrams, and timing documentation.
• Partner with physical design to refine RTL and microarchitecture based on synthesis and timing feedback.
• Contribute to verification planning and debug using waveforms, logs, and assertions.
• Support front-end checks (lint, CDC/RDC, constraint reviews).

Benefits

• Generous Paid Time Off
• 401k Matching
• Retirement Plan
• Visa Sponsorship
• Four Day Work Week
• Generous Parental Leave
• Tuition Reimbursement
• Relocation Assistance