MEMS Analog Mixed Signal Verification Engineer

Role Overview

The position is aimed at Mixed Signal verification engineer with previous experience in analog on top mixed and digital simulations of ASIC. The candidate will be part of Mixed verification team of MEMS sGROUP and will have the opportunity to follow all the ASIC verification process from specification definition up to final product industrialization.

What You Will Do

Definition and development of verification test bench, development of verification components, test case development for simulation, debugging failures and creating simulation cases for various studies.

Why It Might Be a Fit

The ideal candidate has a good knowledge of Analog custom circuit, Modeling languages such as System Verilog RNM, Verilog-AMS, Analog Model definition and implementation, Analog Model verification and validation, Analog, digital and mixed-signal simulation environments and tools, Bugs analysis and reporting.

Requirements

• Good knowledge of Analog custom circuit
• Modeling languages such as System Verilog RNM, Verilog-AMS
• Analog Model definition and implementation
• Analog Model verification and validation
• Analog, digital and mixed-signal simulation environments and tools
• Bugs analysis and reporting

Benefits

• Diverse and inclusive workplace
• No tolerance for discrimination
• Equity in career development and opportunities
• Equal remuneration