MEMS Analog Mixed Signal Verification SR/Team Leader

Role Overview

Join the Mixed verification team of MEMS GROUP and contribute to the development of verification test bench, verification components, and test cases for simulation. Work with cutting-edge verification methodologies on Subsystem and SoC levels.

What You Will Do

Define and develop verification test bench, develop verification components, create test cases for simulation, debug failures, and create simulation cases for various studies.

Why It Might Be a Fit

Ideal candidate has 3-5 years of experience in analog mixed-signal verification, knowledge of Analog custom circuit, simulation environments and tools, and soft skills such as good communication and team working.

Requirements

• 3-5 years of experience in analog mixed-signal verification
• Good knowledge of Analog custom circuit
• Analog, digital and mixed-signal simulation environments and tools
• Bugs analysis and reporting
• Analog SystemVerilog Assertions
• Basic knowledge of Modeling languages such as System Verilog RNM, Verilog-AMS, Analog Model definition and implementation
• Analog Model verification and validation
• Coverage
• Digital logic gates
• Scripting languages like python
• Unified Power Format (UPF) applied to mixed-signal simulations
• Knowledge of SystemVerilog and UVM methodology, tools and environments for mixed-signal simulations Cadence based
• Communication protocols in mixed simulations (e.g. I2C, SPI and I3C)
• Formal tools for top-level connectivity
• Version control system

Benefits

• Diverse and inclusive workplace
• No tolerance for discrimination
• Equity in career development and opportunities
• Equal remuneration
• Opportunities for growth and learning