IP Design Technical Lead/ Staff ASIC RTL Design Engineer

Join Synopsys as an IP Design Technical Lead/ Staff ASIC RTL Design Engineer in Bengaluru, India. The role involves architecting and implementing state-of-the-art RTL designs, mentoring and leading a team of designers, and contributing to cutting-edge innovation.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, or related field.
• 4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.
• Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.
• Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.
• Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler.
• Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.
• Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).
• Exposure to quality processes in IP design and verification is an advantage.
• Prior experience as a technical lead or mentor is highly desirable.

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Monetary and non-monetary offerings