Principal Engineer - ASIC Digital Design IP Development (Ethernet/UALink Protocols)

Principal Engineer - ASIC Digital Design IP Development (Ethernet/UALink Protocols) position at Synopsys in Bengaluru, India. The role involves architecting and designing state-of-the-art RTL for DesignWare IP cores, collaborating with verification teams, and mentoring junior engineers.

Requirements

• Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE)
• 12+ years of relevant ASIC design experience
• Expertise in protocols such as UALink, Ethernet, DDR, PCIe, USB
• Proficiency in synthesizable Verilog/System Verilog RTL coding, simulation, and design verification tools
• Strong background in lint, CDC, synthesis, static timing analysis, formal checking, and P&R-aware synthesis flows

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Total rewards including monetary and non-monetary offerings