Senior Staff RTL Design Engineer

Role Overview

Design and code RTL for high-speed Ethernet IP cores, translate protocol specifications into micro-architecture and detailed design documents, and perform technical reviews of functional specs and RTL code.

What You Will Do

Design and code RTL for high-speed Ethernet IP cores, build and refine directed Verilog testbenches, and drive timing analysis and closure for high-speed designs.

Why It Might Be a Fit

The ideal candidate will have deep RTL design experience, strong working knowledge of at least one protocol, and proven ability to create micro-architecture and detailed design documents.

Requirements

• Bachelor's in Electrical Engineering with 8+ years of hands-on ASIC or IP design experience, or Master's with 6+ years
• Deep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers
• Strong working knowledge of at least one protocol from this list: AMBA (AHB, AXI, CHI), SD, eMMC, DDR, PCIe, USB, MIPI
• Proven ability to create micro-architecture and detailed design documents from functional specs for small to medium complexity blocks
• Hands-on experience with Verilog or SystemVerilog, simulation tools, synthesis flows, static timing analysis, lint, CDC, and formal verification tools

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Monetary and non-monetary offerings
• Salary range and benefits details will be provided during the hiring process