Senior Staff RTL Design Engineer

Role Overview

We are seeking a Senior Staff RTL Design Engineer to join our dynamic engineering team at Synopsys Bangalore. The successful candidate will be responsible for designing and implementing high-performance mixed signal IP blocks, including UCIe, DDR, and Die-to-Die interfaces. The role requires strong technical expertise in RTL design, synthesis, timing, and DFT, as well as excellent communication and collaboration skills.

What You Will Do

The Senior Staff RTL Design Engineer will own RTL design and implementation for high-performance mixed signal IP blocks, develop microarchitecture from specification, drive design reviews, and take technical ownership of assigned blocks through tape-out. The role also involves writing synthesizable Verilog and SystemVerilog, collaborating with analog designers, verification engineers, physical design teams, and validation leads, and driving synthesis, lint, CDC analysis, DFT insertion, and timing closure using industry-standard EDA tools.

Why It Might Be a Fit

This role is ideal for a seasoned engineer who has spent years designing silicon that actually ships, not just passes simulation. The successful candidate will have a strong understanding of synthesizable constructs and coding for performance, as well as experience with logic synthesis, static timing analysis, CDC, and DFT concepts. The role offers opportunities for mentorship, collaboration, and innovation, and the team prides itself on technical excellence, collaboration, and innovation.

Requirements

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or equivalent
• 8+ years of hands-on experience in RTL design for IP, ASIC, or SoC development
• Strong proficiency in Verilog and SystemVerilog for RTL coding
• Deep understanding of synthesizable constructs and coding for performance
• Solid experience with logic synthesis, static timing analysis, CDC, and DFT concepts
• Familiarity with industry-standard EDA tools
• Proven ability to debug complex functional and timing issues across large, multi-block designs
• Experience with scripting in Python, TCL, or Perl to automate flows and improve productivity

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Monetary and non-monetary offerings
• Salary range and benefits details will be provided during the hiring process