Staff RTL Design Engineer

Staff ASIC Digital Design Engineer at Synopsys, responsible for implementing RTL designs in Verilog for SERDES interfaces and IP cores, running Spyglass CDC/RDC/Lint and Tmax to catch clock/reset domain issues, and creating synthesis constraints for robust ASIC implementations.

Requirements

• B.E/B.Tech/M.Tech in Electronics & Communication Engineering, Electrical Engineering, or a related field.
• At least 3 years of hands-on ASIC digital design experience, especially with HDL coding in Verilog.
• Solid skills in building and debugging synthesis constraints, and a working knowledge of Static Timing Analysis (STA).
• Experience with Spyglass CDC/RDC/Lint and Tmax for code quality and domain crossing checks.
• Practical ability to script in Perl, Shell, Python, or Tcl for automating design and verification tasks.
• Familiarity with high-speed SERDES protocols and RTL implementation is a strong plus.

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Total rewards including monetary and non-monetary offerings