Staff Verification Engineer

We're looking for a Verification Engineer to contribute to our next generation connectivity networking products. The ideal candidate will have a strong background in RTL verification methodologies, UVM, C, and SystemVerilog.

Requirements

• Multi-year experience in Design SoC Verification
• Experience in SerDes PHY, DSP, and Analog mixed signal is desirable
• Knowledge in Ethernet and PCIe standards is desirable
• An applied understanding of UVM and verification techniques
• Experience with constrained-random verification in System Verilog and UVM
• Formal Verification, and Power-aware UPF verification techniques
• Post-Silicon Debug: Experience in post-silicon bring-up and debugging
• Communication & Leadership: Team player with strong communication skills to ensure effective program execution

Benefits

• Comprehensive health plans
• Wellness Spending Account (WSA)
• Employee Assistance Program (EAP)
• Paid Vacation
• Paid Holidays
• Parental Leave