Emulation Verification Engineer

The Emulation Verification Engineer will participate in verifying large Wireless SoCs using Emulation. This involves porting designs onto Palladium, executing detailed Emulation tests, and developing code for Design verification using Verilog/System Verilog/UVM. The role is crucial for bringing in mixed signal models onto the Palladium platform.

Requirements

• BS and at least 3 years of relevant industry experience.
• Experience with System Verilog, Verilog or UVM.
• Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow.
• Experience in writing Synthesize-able SystemVerilog/Verilog code and SystemVerilog assertions.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Tuition reimbursement
• Reimbursement for educational expenses