SoC Physical Design Engineer, STA/Timing

This position involves working with design teams to debug timing issues, facilitating logic changes, creating timing ECO’s, and maintaining scripts for analysis. The role also focuses on creating documentation and guidelines. The team will analyze timing paths, implement infrastructure, and ensure accurate reporting of timing-related issues.

Requirements

• Minimum Bachelor's degree.
• Experience with STA.
• Experience with noise, crosstalk, and/or OCV effects.
• Familiar with timing of large high-performance SoC designs.
• Programming skills with Perl and TCL
• Experience with large design STA and Timing Closure.
• Good communicator

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products
• Free services
• Educational reimbursement