Senior Emulation/Verification Application Engineer

Join our elite Application Engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at Cadence, a company listed in Fortune magazine and Great Place to Work as one of the 2025 World's Best WorkplacesTM for the sixth time!

Requirements

• FPGA prototyping knowledge including compilation, debug and performance optimization on FPGA prototyping platforms
• Experience with hardware accelerators and emulators
• Education or experience in Verilog, Systemverilog, or related field
• Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing
• Lab or internship experience leveraging hands on experience with lab bring up, debug, chipscope and instrument usage
• Good understanding and knowledge of Object Oriented Programming and experience in one such programming language such as C++, Java, Python or Systemverilog
• Knowledge of Linux/Unix platforms and scripting languages such as Perl, TCL, Python
• Strong verbal and written communication skills in English
• Self-motivated and strong teamwork skills
• Strong problem solving skills

Benefits

• Paid vacation
• Paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• Medical, dental and vision plan options