Lead RTL Engineer (CPU & Processor Design)

Role Overview

We are partnering with an innovative semiconductor company developing next-generation compute technologies. The team is building advanced processor architectures and is seeking an experienced RTL leader to drive implementation from architectural specification through tapeout.

What You Will Do

Design original competition-level mathematics problems, create challenging reasoning tasks, write complete mathematical solutions, and evaluate AI-generated solutions for correctness and logical consistency.

Why It Might Be a Fit

You will play a key role in driving the path from RTL development to successful GDSII handoff, requiring ownership of RTL implementation, synthesis, timing closure, and coordination across architecture, verification, and physical design teams.

Requirements

• 7+ years of RTL design experience using SystemVerilog
• Proven experience leading RTL development for processor, CPU, DSP, or datapath-intensive designs
• Experience delivering at least one silicon tapeout through GDSII handoff
• Strong synthesis and timing closure experience using industry-standard EDA tools
• Deep understanding of microarchitecture and hardware design principles
• Experience with advanced semiconductor process technologies (28nm or below preferred)
• Ability to lead engineering teams while remaining highly hands-on technically
• Strong communication and technical leadership skills