Principal Hardware Design Engineer

Role Overview

We are seeking a Principal Hardware Design Engineer to provide technical leadership and architectural ownership across critical hardware subsystems for next-generation networking products. This role is intended for deeply experienced engineers who operate as technical authorities, drive system-level architecture, resolve the most complex system-level challenges, and elevate the quality and consistency of hardware designs across products.

What You Will Do

Define hardware architecture for complex boards and critical subsystems working with senior architects. Lead system-level HW design strategy, addressing high-speed interconnect architecture, signal integrity and channel strategy, power architecture, sequencing, and margins, reliability, lifecycle, and scale considerations.

Why It Might Be a Fit

As a Principal Hardware Design Engineer, you will play a foundational role in shaping the technical direction of advanced networking platforms, from early architecture through production and sustainment. You will influence multi-team technical decisions while remaining hands-on where it matters most.

Requirements

• Bachelor's or Master's degree in Electronics / Electrical Engineering or a closely related discipline.
• 16+ years of experience in high-performance hardware and system-level design, including multiple products shipped to high-volume production.
• Demonstrated ownership of system or subsystem level architecture within complex networking or compute platforms.
• Deep expertise in high-speed digital design, including signal integrity at scale, SerDes architecture and channel budgeting, NRZ and PAM4 design considerations.
• Strong command of power architecture, including PDN design, sequencing, regulation strategies, and margin analysis.
• Extensive experience with networking hardware platforms, such as switches, routers, or high-performance network appliances.
• Strong familiarity with interfaces and technologies including: DDR4 / DDR5, PCIe (Gen4 / Gen5 or beyond), Ethernet PHYs and MACs (1G → 100G+), SGMII, XAUI, and high-speed SerDes links.
• Working knowledge of PoE architectures, CPU subsystems (ARM, Intel x86, AMD x86), and board-level system integration.
• Proficiency with Cadence PCB tools (OrCAD / Allegro) and strong ability to review and guide complex designs.
• Proven ability to lead system-level debug using advanced lab instrumentation: High-bandwidth oscilloscopes and TDRs, BERTs, DCA, protocol analyzers, JTAG and system debug tools.

Benefits

• Health & Wellbeing
• Personal & Professional Development
• Unconditional Inclusion