Silicon Validation Engineer

Silicon Validation Engineer role at Hewlett Packard Enterprise, responsible for developing and executing chip-level validation tests, with a primary focus on emulator-based and system-level testing. The engineer works closely with senior validation engineers, architecture, design, and software teams to validate ASIC functionality, identify defects, and improve test coverage across multiple product generations.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
• Typically 4–8 years of experience in VLSI validation, verification, or related silicon engineering roles.
• Proficiency with Python programming
• Proficiency in object-oriented programming
• Experience writing tests for integrated circuits
• Proficiency with Linux command-line environments.
• Working knowledge of Verilog or other hardware description languages.
• Experience with ASIC silicon validation or post-silicon testing.
• Working knowledge of high-speed networking concepts and protocols (Ethernet, SERDES fundamentals).

Benefits

• Generous Paid Time Off
• 401k Matching
• Retirement Plan
• Unconditional Inclusion